1. Field of the Invention
The present invention relates to a printed circuit board (PCB) and a method of manufacturing the same. More particularly, the present invention relates to a PCB, in which a hydrophilic fluorine resin coating layer is formed on a resin substrate and a dry plating process is performed instead of a conventional wet plating process, thus obtaining a highly reliable fine circuit, and to a method of manufacturing such a PCB.
2. Description of the Related Art
Presently, PCBs are manufactured using a subtractive process, an MSAP (Modified Semi-Additive Process), or an SAP (Semi-Additive Process).
In particular, a subtractive process is applied to HDI (High Density Interconnection) products, and a subtractive process and an MSAP are used for a UT-CSP (Ultra Thin-Chip Scale Package) and a BGA (Ball Grid Array). In FCBGA (Flip Chip BGA), a subtractive process is applied to a core layer and an SAP is applied to an outer layer, including 2F2B/3F3B (build-up), and further, a seed layer is formed through electroless plating, leading to a fine circuit.
In this regard, the process of manufacturing the PCB according to a first conventional technique is shown in the flowchart of FIG. 1.
Referring to FIG. 1, the method of manufacturing the PCB according to the first conventional technique comprises providing a double-sided copper clad laminate (S101), making a hole (S102), performing desmearing (S103), performing electroless copper plating (S104), performing copper panel electroplating (S105), applying a dry film (S106), performing exposure and development (S107), performing etching (S108), and removing the dry film (S109).
Below, the method of manufacturing the PCB using a subtractive process according to the first conventional technique is specifically described with reference to FIGS. 2A to 2F.
A copper clad laminate (CCL), having a resin insulating layer 11 and copper foils 12 on both surfaces thereof, is prepared and is then subjected to typical etching and drilling to thus form a through hole 13 therein (FIGS. 2A and 2B). Subsequently, the surface of the substrate having the through hole 13 is desmeared, after which an electroless copper layer 14 is formed through electroless plating (FIG. 2C) and a copper panel plating layer 15 is formed through electroplating (FIG. 2D). Then, a dry film 16 is applied on the part of the copper layer that corresponds to a circuit pattern having the through hole 13 (FIG. 2E), and the other unnecessary copper parts are removed through exposure and development, followed by removing the dry film 16, thereby completing the patterning procedure (FIG. 2F).
In addition, the process of manufacturing the PCB according to a second conventional technique is shown in the flowchart of FIG. 3.
As shown in FIG. 3, the method of manufacturing the PCB according to the second conventional technique comprises providing a double-sided CCL (S201), performing half-etching (S202), making a hole (S203), performing desmearing (S204), performing electroless copper plating (S205), applying a dry film (S206), performing exposure and development (S207), performing copper pattern electroplating (S208), removing the dry film (S209), and performing flash etching (S210).
Below, the method of manufacturing the PCB through MSAP according to the second conventional technique is specifically described with reference to FIGS. 4A to 4F.
A CCL, having a resin insulating layer 21 and copper foils 22 on both surfaces thereof, is half-etched (FIG. 4A), and is then subjected to typical etching and drilling to thus form a through hole 23 therein (FIG. 4B). Subsequently, the surface of the substrate having the through hole 23 is desmeared, after which an electroless copper layer 24 is formed through electroless plating (FIG. 4C). A dry film 26 is applied on the part of the copper layer, with the exception of a circuit pattern having the through hole 23 (FIG. 4D). Using such a dry film as a resist, a copper pattern plating layer 27 is formed through electroplating (FIG. 4E). Thereafter, the dry film 26 is removed, and unnecessary copper parts are removed through flash etching, thereby completing the patterning procedure (FIG. 4F).
As such, although the material for the resin insulating layer is typically exemplified by epoxy resin, such as FR-4, BT (Bismaleimide Triazine), or ABF (Ajinomoto Build up Film), it is disadvantageous because it has a high dielectric constant (Dk>3.5[ABF]˜4.5[BT, FR-4]) and a high loss coefficient (Df>0.05), and undesired signal transfer rate and transfer loss are caused, consequently generating heat and deteriorating electrical properties.
For example, in the case of BGA or UT-CSP products through a subtractive process and MSAP using BT insulating material, the surface profile of the material is 1 μm or more, and L/S (line/Space) is limited to a minimum circuit width of 50/50 μm in the subtractive process. On the other hand, in MSAP, variation in the thickness of the copper layer occurs due to half-etching, therefore L/S is limited to a minimum circuit width of 25/25 μm. Ultimately, a fine circuit having a pitch of less than 50 μm (L/S=25/25 μm) is difficult to realize.
Further, in the group of FCBGA products, a multilayered substrate is manufactured through SAP using ABF insulating material. That is, as shown in FIG. 5, a core layer (which is composed of 1st and 2nd layers) is formed through a subtractive process, and outer layers (which are composed of 3rd to 6th layers) are formed through SAP, including electroless plating for the formation of a plating layer 1˜3 μm thick, circuit formation, electroplating, stripping, and flash etching, which are repeated two times. Thereby, through holes 33 and circuit patterns 32a, 32b, 35a, 35b, 37a, 37b are formed in resin insulating layers 31, 34a, 34b, 36a, 36b. Further, solder resists 38a, 38b are applied, and solder resist open parts 39a, 39b are formed, thereby manufacturing a FCBGA substrate having a total of six layers.
However, due to the use of expensive ABF material, the process cost is increased, leading to a high production price. In the case where SAP is used, since the surface profile of the ABF material is 1 μm or greater, the surface roughness is large and the pitch (line/space) is 18/18 μm. Furthermore, a fine circuit is difficult to realize, attributable to wet surface treatment and electroless chemical plating.
With the demand for light, slim, short and small PCBs, various manufacturers have developed insulating materials for realizing a fine circuit and exhibiting high functionality to thus increase the signal transfer rate of the circuit. In the present development trend, since the input and output of signals are increased, the circuit is required to be fine. Accordingly, among high functional insulating materials, insulating material having a low dielectric constant and a low loss coefficient, such as PTFE (PolyTetraFluoroEthylene), PI (PolyImide), LCP (Liquid Crystal Polymer), bonding sheet, or TPI (Thermoplastic PolyImide), is used to increase the signal transfer rate. In addition, the surface roughness of the material is controlled to 0.5 μm or less so as to enable the formation of a fine circuit even when using SAP. However, in the conventional SAP, since the copper layer is formed through a wet process such as wet surface treatment and electroless plating, the surface roughness is enlarged, and the formation of the fine circuit is limited. As well, a lot of waste is generated, therefore the above process is considered environmentally unfriendly.